The present invention relates generally to integrated circuit technology and more particularly to using various properties of light in the making of integrated circuits.
As semiconductor technology progresses, the dimensions of features, for example, line widths, gate dimensions, etc., in integrated circuits are shrinking. Many obstacles must be overcome in order to process an integrated circuit with features of these dimensions. One such problem exists in photolithography because the featured dimensions are too small relative to the wavelength of the light being used. Phase shift masks provide a technique for alleviating this problem by providing desirable destructive interference at the areas where the fine dimensions are present. This approach results in other problems associated with leaving under-exposed photoresist in areas where the photoresist was intended to be fully exposed. One known solution of this problem is the use of a complementary phase shift mask (CPSM) process which is also called alternating aperture phase shift mask (AAPSM) process.
Some disadvantages of phase shift masks and of the CPSM process are exemplified by reference to a desired pattern of gate electrodes 14 and 16 as shown in FIG. 1. Typically, such gate electrodes are the finest dimensions on the integrated circuit and are polysilicon. Thus the most advanced lithographic techniques are typically applied to polysilicon, but it could be a different gate material, and it could be a different purpose than for gates. Using a phase shift mask to attempt to achieve this desired pattern, begins with the formation of a phase shift mask 20 having phase shifting regions 22 and 30 and a transparent region 28 formed on a plate which is transparent to the light used to expose photoresist, for example, a quartz plate for deep ultraviolet light, as shown in FIG. 2. The difference between phase shifting regions 30 and 22 and the transparent region 28 is the thickness of the plate. Typically, phase shifting regions 22 and 30 are thinned down regions of the plate, and transparent region 28 is not typically thinned. The plate passes light which is referenced to be at a phase angle of 0xc2x0 and the phase shifting region passes light which is 180xc2x0 out of phase with the 0xc2x0 light. The 0xc2x0 light has a non-zero light intensity that alters a property of the photoresist. Additionally the 180xc2x0 light also has a non-zero light intensity and alters a property of the photoresist in a manner identical to the 0xc2x0 light. In the region between the 0xc2x0 light and the 180xc2x0 light, light destructively interferes to form a xe2x80x9cdarkxe2x80x9d area of low light intensity. This is the desirable feature of phase shift mask techniques. On mask 20, regions 24 and 26 correspond to the intended dark regions on the photoresist-covered wafer, are formed out of chromium or another opaque material, and are positioned between phase shifting region 30 or 22 and transparent region 28.
Developing semiconductor wafer 10 with phase shift mask 20, however, results in semiconductor 10 shown in FIG. 3. Gate electrode regions 16 and 14 have been patterned as desired. However a polysilicon phase conflict region 32 exists which arises from under-exposed photoresist as well. At the boundary between the 0 degrees and 180 degrees phase-shifted light there is destructive interference so that the photoresist in this boundary region may not be sufficiently exposed. The result of such insufficient exposure is that the photoresist in that area is not removed so that the subsequent etch of polysilicon results in an undesirable polysilicon phase conflict region 32 being formed. The result is that the very aspect of destructive interference that is desirable for gate formation has a similar effect at the boundary between the 0 degrees and 180 degrees phase shifting regions such as regions 30 and 28. Although, region 32 is undesirable as shown, there may be other situations where a similar region formed at a boundary between 0 degrees and 180 degrees regions may be used to advantage, for example, to form a thin gate. For general designs, such so-called phase conflicts are mathematically unavoidable.
The CPSM process was developed to prevent this undesirable polysilicon phase conflict region 32 arising from the 0 degrees and 180 degrees boundaries. The CPSM process adds a second, binary mask which is complementary to phase shift mask 20 for use in an exposure subsequent to that using phase shift mask 20. This second mask exposure occurs before the etch of the polysilicon so that the polysilicon region 32 is not actually formed. Region 32, however, does correspond to an under exposed portion of the photoresist after exposure using mask 20. The binary mask is opaque everywhere with regard to FIG. 3 except over polysilicon phase conflict region 32. Thus, after exposing semiconductor wafer 10 with the binary mask, removing the exposed photoresist, and etching the polysilicon, the desired semiconductor feature 10 of FIG. 1 may be substantially achieved. Due to alignment problems between mask 20 and the complementary mask, it is likely that either some portion of region 32 be present or some portion of region 16 not be present, and in either case resulting in a somewhat different pattern than the desired pattern.
As discussed, in the solution provided by the CPSM process, the semiconductor wafer undergoes two exposures using different masks. This is disadvantageous in a semiconductor-processing environment because it increases cycle time and requires highly accurate alignment of two mask exposures. In addition the additional mask is an added cost. Accordingly, there is need for improvement over phase shift mask technology as it currently exists.